Invention Grant
- Patent Title: Integrating and accessing passive components in wafer-level packages
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Application No.: US16635146Application Date: 2017-09-29
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Publication No.: US11646288B2Publication Date: 2023-05-09
- Inventor: Gianni Signorini , Veronica Sciriha , Thomas Wagner
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/054533 2017.09.29
- International Announcement: WO2019/066945A 2019.04.04
- Date entered country: 2020-01-29
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/31 ; H01L23/538

Abstract:
In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.
Public/Granted literature
- US20210057367A1 INTEGRATING AND ACCESSING PASSIVE COMPONENTS IN WAFER-LEVEL PACKAGES Public/Granted day:2021-02-25
Information query
IPC分类: