Invention Grant
- Patent Title: Error correction for dynamic data in a memory that is row addressable and column addressable
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Application No.: US16827235Application Date: 2020-03-23
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Publication No.: US11657889B2Publication Date: 2023-05-23
- Inventor: Jawad B. Khan , Richard L. Coulson , Zion S. Kwok , Ravi H. Motwani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G11C29/44 ; G11C11/409 ; G11C5/02 ; G11C29/02 ; G11C29/12

Abstract:
Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.
Public/Granted literature
- US20200219580A1 ERROR CORRECTION FOR DYNAMIC DATA IN A MEMORY THAT IS ROW ADDRESSABLE AND COLUMN ADDRESSABLE Public/Granted day:2020-07-09
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