Invention Grant
- Patent Title: Nonvolatile semiconductor memory device which performs improved erase operation
-
Application No.: US17344146Application Date: 2021-06-10
-
Publication No.: US11664077B2Publication Date: 2023-05-30
- Inventor: Jun Nakai , Noboru Shibata
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP 10182485 2010.08.17
- The original application number of the division: US15666114 2017.08.01
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/16 ; G11C16/14 ; G11C16/34 ; G11C16/26

Abstract:
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
Public/Granted literature
- US20210304821A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION Public/Granted day:2021-09-30
Information query