- 专利标题: Stacked semiconductor package and packaging method thereof
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申请号: US17210452申请日: 2021-03-23
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公开(公告)号: US11670622B2公开(公告)日: 2023-06-06
- 发明人: Yin-Huang Kung , Chia-Hung Lin , Fu-Yuan Yao , Chun-Wu Liu
- 申请人: Powertech Technology Inc.
- 申请人地址: TW Hukou Township, Hsinchu County
- 专利权人: Powertech Technology Inc.
- 当前专利权人: Powertech Technology Inc.
- 当前专利权人地址: TW Hukou Township
- 代理机构: patenttm.us
- 优先权: TW 9140719 2020.11.20
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L25/00
摘要:
A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.
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