- 专利标题: Bump-on-trace interconnect
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申请号: US17102073申请日: 2020-11-23
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公开(公告)号: US11682651B2公开(公告)日: 2023-06-20
- 发明人: Chen-Hua Yu , Chen-Shien Chen
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater Matsil, LLP
- 分案原申请号: US13653618 2012.10.17
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L25/065 ; H01L25/00
摘要:
Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
公开/授权文献
- US20210074673A1 Bump-on-Trace Interconnect 公开/授权日:2021-03-11
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