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公开(公告)号：US20200117874A1
公开(公告)日：2020-04-16
申请号：US16710478
申请日：2019-12-11
发明人： Chen-Hua Yu , Yu-Feng Chen , Chih-Hua Chen , Hao-Yi Tsai , Chung-Shi Liu
IPC分类号： G06K9/00 , H01L25/16 , H01L23/00 , H01L23/498 , H01L23/48 , H01L23/31 , H01L21/768 , H01L21/56
摘要： A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
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公开(公告)号：US20190067179A1
公开(公告)日：2019-02-28
申请号：US16108535
申请日：2018-08-22
发明人： Chia-Ching Tsai , Yi-Wei Chiu , Hung Jui Chang , Li-Te Hsu
IPC分类号： H01L23/498 , H01L21/768
摘要： A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the porous dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the porous dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.
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3.发明申请公开(公告)号：US20190252294A1
公开(公告)日：2019-08-15
申请号：US16390669
申请日：2019-04-22
发明人： Cheng-Chieh Hsieh , Chi-Hsi Wu , Shin-Puu Jeng , Tsung-Yu Chen , Wensen Hung
IPC分类号： H01L23/427 , H01L23/367 , H01L25/10 , H01L23/00
CPC分类号： H01L23/4275 , H01L23/3128 , H01L23/3675 , H01L23/427 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/9222
摘要： Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.
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公开(公告)号：US20240365685A1
公开(公告)日：2024-10-31
申请号：US18771255
申请日：2024-07-12
发明人： Shy-Jay LIN , Mingyuan SONG
摘要： A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer, as a magnetic free layer, disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. The first magnetic layer includes a lower magnetic layer, a middle layer made of non-magnetic layer and an upper magnetic layer.
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公开(公告)号：US20240365680A1
公开(公告)日：2024-10-31
申请号：US18764426
申请日：2024-07-05
发明人： Mauricio Manfrini
IPC分类号： H10N50/80 , H01L23/522 , H10B61/00 , H10N50/01 , H10N50/10
CPC分类号： H10N50/80 , H01L23/5226 , H10B61/00 , H10N50/01 , H10N50/10
摘要： The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.
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公开(公告)号：US20240365550A1
公开(公告)日：2024-10-31
申请号：US18769334
申请日：2024-07-10
IPC分类号： H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B43/10
CPC分类号： H10B43/27 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B43/10
摘要： A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the multi-layer stack, a charge storage layer disposed between the conductive layers and the channel layer, a first conductive pillar and a second conductive pillar adjacent to the channel layer, a first interconnect structure connected to an end of the first conductive pillar, and a second interconnect structure connected to an end of the second conductive pillar. The end of the first conductive pillar connected to the first interconnect structure and the end of the second conductive pillar connected to the second interconnect structure are located on opposite sides of the multi-layer stack.
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7.发明公开公开(公告)号：US20240364341A1
公开(公告)日：2024-10-31
申请号：US18767158
申请日：2024-07-09
IPC分类号： H03K19/0185 , H03K3/037
CPC分类号： H03K19/018521 , H03K3/037
摘要： A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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公开(公告)号：US20240363765A1
公开(公告)日：2024-10-31
申请号：US18306488
申请日：2023-04-25
发明人： Gerben Doornbos , Georgios Vellianitis , Marcus Johannes Henricus Van Dal , Yu-Ming Lin , Oreste Madia
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7883 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： Some embodiments relate to an integrated device, including a control gate over a substrate, the control gate having a first length; a tunnel dielectric on the control gate; a floating gate having a second length on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; a channel on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and source/drain terminals on the channel, wherein the first length of the control gate is less than the second length of the floating gate.
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9.发明公开公开(公告)号：US20240363762A1
公开(公告)日：2024-10-31
申请号：US18769998
申请日：2024-07-11
发明人： Yong-Jie Wu , Hui-Hsien Wei , Yen-Chung Ho , Mauricio Manfrini , Chia-Jung Yu , Chung-Te Lin , Pin-Cheng Hsu
IPC分类号： H01L29/786 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/401 , H01L29/41733 , H01L29/41775 , H01L29/42364 , H01L29/42384 , H01L29/66742 , H01L29/78618 , H01L29/7869
摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.
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公开(公告)号：US20240363744A1
公开(公告)日：2024-10-31
申请号：US18139070
申请日：2023-04-25
发明人： Fu-Ting YEN , Yu-Yun PENG , Kuei-Lin CHAN
IPC分类号： H01L29/775 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/775 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545
摘要： A semiconductor device includes a substrate, a first active structure, a second active structure, a wall and a STI layer. The first active structure is formed on the substrate. The second active structure is formed on the substrate. The wall is formed between the first active structure and the second active structure. The STI layer is formed adjacent to the first active structure and has an upper surface. A distance between a spacer of the first active structure and the upper surface of the STI layer may range between 0 and 50 nanometers.
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