Invention Grant
- Patent Title: Standard cell architecture with power tracks completely inside a cell
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Application No.: US16263093Application Date: 2019-01-31
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Publication No.: US11682664B2Publication Date: 2023-06-20
- Inventor: Srinivasa Chaitanya Gadigatla , Ranjith Kumar , Marni Nabors , Quan Phan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L23/528 ; H01L27/118 ; G06F30/394
Abstract:
An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.
Public/Granted literature
- US20200251464A1 STANDARD CELL ARCHITECTURE WITH POWER TRACKS COMPLETELY INSIDE A CELL Public/Granted day:2020-08-06
Information query
IPC分类:
