公开(公告)号：US20230207491A1

公开(公告)日：2023-06-29

申请号：US17561353

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Kimberly Pierce ,  Marni Nabors ,  Mark Phillips

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06 ,  G03F7/20

CPC classification number: H01L23/585 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0611 ,  G03F7/2004

Abstract: Devices, systems, and methods are described related to providing nonlinear lithographic seams, such as rectilinear lithographic seams, between adjacent fields of an integrated circuit die. Such nonlinear lithographic seams include lithographic enabling structures formed in co-planar layers with respect to functional structures in functional units of the fields of the integrated circuit die. Providing nonlinear lithographic seams improves layout efficiency of the functional units of the integrated circuit die.

公开(公告)号：US20250006591A1

公开(公告)日：2025-01-02

申请号：US18217022

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Nischal Arkali Radhakrishna ,  Chinhsuan Chen ,  Sivakumar Venkataraman ,  Somashekar Bangalore Prakash ,  Marni Nabors

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: An integrated circuit (IC) device may include standard cells with multiple parallel paths interconnecting transistors at a device level and over a transistor, in a higher layer of an interconnect structure. The parallel paths may include multiple power supply via contacts on a transistor source structure and multiple supply interconnect lines over the transistor and coupling the transistor to an associated power supply. The parallel paths may include multiple output via contacts on an integrated transistor drain structure and multiple output interconnect lines over a complementary transistor device. The parallel paths may include separate, rather than shared or integrated, adjacent source structures coupled to a same power supply.

公开(公告)号：US11373999B2

公开(公告)日：2022-06-28

申请号：US16002723

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Yih Wang ,  Rishabh Mehandru ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Mark Bohr ,  Marni Nabors

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US20240096791A1

公开(公告)日：2024-03-21

申请号：US18520872

申请日：2023-11-28

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro J. Kobrinsky ,  Marni Nabors

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L23/528 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3128 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L23/5226

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

公开(公告)号：US11682664B2

公开(公告)日：2023-06-20

申请号：US16263093

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Srinivasa Chaitanya Gadigatla ,  Ranjith Kumar ,  Marni Nabors ,  Quan Phan

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/118 ,  G06F30/394

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/11803 ,  G06F30/394

Abstract: An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.

公开(公告)号：US11410928B2

公开(公告)日：2022-08-09

申请号：US16003031

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro Kobrinsky ,  Marni Nabors

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/522 ,  H01L23/00

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

公开(公告)号：US20250112167A1

公开(公告)日：2025-04-03

申请号：US18375327

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Kimberly Pierce ,  Marni Nabors ,  Nidhi Khandelwal ,  Keith Zawadzki

IPC: H01L23/544 ,  G03F7/09 ,  H01L21/768 ,  H01L23/528 ,  H01L23/58

Abstract: An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as registration marks and metrology structures. The multiple lithographic fields may be or include high numerical aperture extreme ultraviolet lithographic fields. The lithographic seam may interface with wafer finishing collaterals (such as guard rings).

公开(公告)号：US20250107243A1

公开(公告)日：2025-03-27

申请号：US18473440

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Burak Baylav ,  Prabhjot Luthra ,  Nidhi Khandelwal ,  Marni Nabors

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528

Abstract: An IC device may include functional regions as well as replica cells and filler cells that can reduce local layout effect in the IC device. A functional region includes functional cells, e.g., logic cell or memory cells. A white space may be between a first functional region and a second functional region. A first portion of the white space may be filled with replica cells, each of which is a replica of a cell in the first functional region. A second portion of the white space may be filled with filler cells that are not functional. The first function region is closer to the replica cells than to the filler cells. A third portion of the white space may be filled with replica cells, each of which is a replica of a cell in the second functional region. The second portion is between the first portion and the third portion.

公开(公告)号：US11881452B2

公开(公告)日：2024-01-23

申请号：US17843395

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro J. Kobrinsky ,  Marni Nabors

IPC: H01L21/762 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3128 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

公开(公告)号：US20220319978A1

公开(公告)日：2022-10-06

申请号：US17843395

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro J. Kobrinsky ,  Marni Nabors

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.