Invention Grant
- Patent Title: Integrated circuit structure and method for reducing polymer layer delamination
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Application No.: US17382565Application Date: 2021-07-22
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Publication No.: US11688728B2Publication Date: 2023-06-27
- Inventor: Jing-Cheng Lin , Jui-Pin Hung , Hsien-Wen Liu , Min-Chen Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- The original application number of the division: US13901311 2013.05.23
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L23/525 ; H01L25/065 ; H01L23/498 ; H01L23/00 ; H01L23/31 ; H01L23/532 ; H01L23/538 ; H01L21/56

Abstract:
An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
Public/Granted literature
- US20210351173A1 Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination Public/Granted day:2021-11-11
Information query
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