- 专利标题： Transistor and methods of forming integrated circuitry
-
申请号： US17317674申请日： 2021-05-11
-
公开(公告)号： US11688808B2公开(公告)日： 2023-06-27
- 发明人: Hung-Wei Liu , Sameer Chhajed , Jeffery B. Hull , Anish A. Khandekar
- 申请人： Micron Technology, Inc.
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Wells St. John P.S.
- 分案原申请号： US16536590 2019.08.09
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L29/66 ; H01L21/02 ; H01L29/04 ; H10B12/00
摘要：
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.
公开/授权文献
- US20210265502A1 Transistor And Methods Of Forming Integrated Circuitry 公开/授权日：2021-08-26
信息查询
IPC分类:
