Invention Grant
- Patent Title: D flip-flop
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Application No.: US17973740Application Date: 2022-10-26
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Publication No.: US11689190B2Publication Date: 2023-06-27
- Inventor: Yu-Hao Liu , Sheng-Hua Chen , Cheng-Hsing Chien
- Applicant: FARADAY TECHNOLOGY CORPORATION
- Applicant Address: TW Hsinchu
- Assignee: FARADAY TECHNOLOGY CORPORATION
- Current Assignee: FARADAY TECHNOLOGY CORPORATION
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Priority: TW 9142660 2020.12.03
- The original application number of the division: US17722669 2022.04.18
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/012 ; H03K3/037

Abstract:
A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.
Public/Granted literature
- US20230048943A1 D FLIP-FLOP Public/Granted day:2023-02-16
Information query
IPC分类: