公开(公告)号：US11515862B2

公开(公告)日：2022-11-29

申请号：US17722669

申请日：2022-04-18

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao Liu ,  Sheng-Hua Chen ,  Cheng-Hsing Chien

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US11342904B1

公开(公告)日：2022-05-24

申请号：US17184640

申请日：2021-02-25

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao Liu ,  Sheng-Hua Chen ,  Cheng-Hsing Chien

IPC: H03K3/012 ,  H03K3/356

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US11689190B2

公开(公告)日：2023-06-27

申请号：US17973740

申请日：2022-10-26

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao Liu ,  Sheng-Hua Chen ,  Cheng-Hsing Chien

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/037

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.