Invention Grant
- Patent Title: Techniques for memory access in a reduced power state
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Application No.: US17522294Application Date: 2021-11-09
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Publication No.: US11698673B2Publication Date: 2023-07-11
- Inventor: Binata Bhattacharyya , Paul S. Diefenbaugh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: KDW Firm PLLC
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/3287 ; G06F1/3206 ; G06F3/06 ; G06F9/30 ; G06F12/06

Abstract:
Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.
Public/Granted literature
- US20220066535A1 TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE Public/Granted day:2022-03-03
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