Invention Grant
- Patent Title: Device package
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Application No.: US17347220Application Date: 2021-06-14
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Publication No.: US11705412B2Publication Date: 2023-07-18
- Inventor: Cheng-Nan Lin , Wei-Tung Chang , Jen-Chieh Kao , Huei-Shyong Cho
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Main IPC: H01L23/66
- IPC: H01L23/66 ; H01L23/31 ; H01L23/498 ; H01L21/48 ; H01Q1/22 ; H01L23/00 ; H01Q1/24
Abstract:
An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
Public/Granted literature
- US20210305181A1 DEVICE PACKAGE Public/Granted day:2021-09-30
Information query
IPC分类:
