Invention Grant
- Patent Title: Performing scrambling operations based on a physical block address of a memory sub-system
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Application No.: US17489405Application Date: 2021-09-29
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Publication No.: US11709622B2Publication Date: 2023-07-25
- Inventor: Fangfang Zhu , Juane Li , Seungjune Jeon , Jiangli Zhu , Ying Tai
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06

Abstract:
Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.
Public/Granted literature
- US20220100416A1 PERFORMING SCRAMBLING OPERATIONS BASED ON A PHYSICAL BLOCK ADDRESS OF A MEMORY SUB-SYSTEM Public/Granted day:2022-03-31
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