公开(公告)号：US12019915B2

公开(公告)日：2024-06-25

申请号：US17703902

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1076

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US20220283744A1

公开(公告)日：2022-09-08

申请号：US17703902

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US20240377990A1

公开(公告)日：2024-11-14

申请号：US18673228

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US11709729B2

公开(公告)日：2023-07-25

申请号：US17489409

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Juane Li ,  Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai

IPC: G06F11/10 ,  G06F21/60 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1068 ,  G06F21/602

Abstract: System and methods are disclosed including a plurality of memory devices and a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising: receiving, from a host system, encrypted write data appended with error-checking data; determining whether the encrypted write data contains an error based on the error-checking data; and responsive to determining that the encrypted write data contains an error, notifying the host system that the encrypted write data contains an error.

公开(公告)号：US11709622B2

公开(公告)日：2023-07-25

申请号：US17489405

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Juane Li ,  Seungjune Jeon ,  Jiangli Zhu ,  Ying Tai

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.

公开(公告)号：US20230082636A1

公开(公告)日：2023-03-16

申请号：US17476701

申请日：2021-09-16

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Ying Tai ,  Fangfang Zhu ,  Juane Li

IPC: G06F11/14

Abstract: A system and method for recovery data generation for partial memory block modifications. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a command to modify a portion of a memory block that is stored by the memory device, wherein the command comprises user data and a location in the memory block; reading user data at the location and existing recovery data for the memory block; generating recovery data for the memory block based on the existing recovery data, the user data at the location, and the user data of the command; and writing the user data of the command and the generated recovery data to the memory device, wherein the user data overwrites the portion of the memory block at the location.

公开(公告)号：US20220100603A1

公开(公告)日：2022-03-31

申请号：US17489409

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Juane Li ,  Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai

IPC: G06F11/10 ,  G06F3/06 ,  G06F21/60

Abstract: System and methods are disclosed including a plurality of memory devices and a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising: receiving, from a host system, encrypted write data appended with error-checking data; determining whether the encrypted write data contains an error based on the error-checking data; and responsive to determining that the encrypted write data contains an error, notifying the host system that the encrypted write data contains an error.

公开(公告)号：US20220100416A1

公开(公告)日：2022-03-31

申请号：US17489405

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Juane Li ,  Seungjune Jeon ,  Jiangli Zhu ,  Ying Tai

IPC: G06F3/06

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.