A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.