-
公开(公告)号：US20230153116A1
公开(公告)日：2023-05-18
申请号：US17981617
申请日：2022-11-07
Applicant: Google LLC
Inventor： Rahul Nagarajan , Suvinay Subramanian , Arpith Chacko Jacob , Christopher Leary , Thomas James Norrie , Thejasvi Magudilu Vijayaraj , Hema Hariharan
CPC classification number: G06F9/3895 , G06F9/3887 , G06F9/30036 , G06N3/02
Abstract: Aspects of the disclosure provide for an accelerator capable of accelerating data dependent, irregular, and/or memory-bound operations. An accelerator as described herein includes a programmable engine for efficiently executing computations on-chip that are dynamic, irregular, and/or memory-bound, in conjunction with a co-processor configured to accelerate operations that are predictable in computational load and behavior on the co-processor during design and fabrication.
-
2.发明申请公开(公告)号：US20210286419A1
公开(公告)日：2021-09-16
申请号：US16818493
申请日：2020-03-13
Applicant: Google LLC
Inventor： Houle Gan , Thomas James Norrie , Gregory Sizikov , Georgios Konstadinidis
Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.
-
公开(公告)号：US20240211264A1
公开(公告)日：2024-06-27
申请号：US18595866
申请日：2024-03-05
Applicant: Google LLC
IPC: G06F9/38
CPC classification number: G06F9/3802 , G06F9/3887
Abstract: Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.
-
4.发明授权公开(公告)号：US11720158B2
公开(公告)日：2023-08-08
申请号：US16818493
申请日：2020-03-13
Applicant: Google LLC
Inventor： Houle Gan , Thomas James Norrie , Gregory Sizikov , Georgios Konstadinidis
Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.
-
公开(公告)号：US11972263B2
公开(公告)日：2024-04-30
申请号：US17972681
申请日：2022-10-25
Applicant: Google LLC
IPC: G06F9/38
CPC classification number: G06F9/3802 , G06F9/3887
Abstract: Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.
-
Patent Agency Ranking
公开(公告)号：US20220269297A1
公开(公告)日：2022-08-25
申请号：US17744025
申请日：2022-05-13
Applicant: Google LLC
Inventor： Robert Ashby Armistead, III , Shuai Jiang , Binayak Roy , Thomas James Norrie , Houle Gan
Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.
-
公开(公告)号：US11334103B2
公开(公告)日：2022-05-17
申请号：US16996405
申请日：2020-08-18
Applicant: Google LLC
Inventor： Robert Ashby Armistead, III , Shuai Jiang , Binayak Roy , Thomas James Norrie , Houle Gan
Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.
-
公开(公告)号：US20240272904A1
公开(公告)日：2024-08-15
申请号：US18109583
申请日：2023-02-14
Applicant: Google LLC
Inventor： Matthew Leever Hedlund , Christopher Aaron Clark , Andrew Everett Phelps , Thomas James Norrie , Sushma Honnavara-Prasad , Vinayak Anand Gokhale , Pareesa Ameneh Golnari
CPC classification number: G06F9/30036 , G06F9/30032 , G06F17/16
Abstract: In a system including vector registers storing right-hand side data and left-hand side data, first and second matrix staging registers, and a systolic array of processing cells for conducting matrix multiplication operations using the right-hand side data and left-hand side data, one or more processors load the right-hand side data from the vector registers to the first matrix staging register based on an instruction indicating whether to transpose the right-hand side data, load the left-hand side data from the vector registers into the second matrix staging register based on another instruction indicating whether to transpose the left-hand side data, load the right-hand side data from the first matrix staging register into the systolic array, and, in a cycle of the matrix multiplication operation, pass one or more columns of the left-hand side data from the second matrix staging register to a column of the systolic array.
-
公开(公告)号：US20230161592A1
公开(公告)日：2023-05-25
申请号：US17972681
申请日：2022-10-25
Applicant: Google LLC
IPC: G06F9/38
CPC classification number: G06F9/3802 , G06F9/3887
Abstract: Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.
-
公开(公告)号：US20220057823A1
公开(公告)日：2022-02-24
申请号：US16996405
申请日：2020-08-18
Applicant: Google LLC
Inventor： Robert Ashby Armistead, III , Shuai Jiang , Binayak Roy , Thomas James Norrie , Houle Gan
IPC: G05F1/575
Abstract: A programmable thermal dissipation power (TDP) system with integrated circuits is provided. The programmable TDP system includes a software interface, a monitoring circuit, and a controller circuit. The monitoring circuit may provide for the instantaneous input power supplied to the system. The controller circuit may monitor both the target TDP information specified from upstream and the input power readings. The controller circuit may generate a pulse-width modulation (PWM) signal that corresponds to a gap between the two power levels and sends the signal to the integrated circuits on the system. The integrated circuit may respond to the change in the input PWM signal and may adjust its power consumption. For example, the integrated circuit may adjust the clock frequency, adjust the instruction rate, skip a number of clock cycles, etc.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.012 seconds)
