公开(公告)号：US11720158B2

公开(公告)日：2023-08-08

申请号：US16818493

申请日：2020-03-13

Applicant: Google LLC

Inventor： Houle Gan ,  Thomas James Norrie ,  Gregory Sizikov ,  Georgios Konstadinidis

IPC: G06F1/28 ,  G06N20/00

CPC classification number: G06F1/28 ,  G06N20/00

Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.

公开(公告)号：US20230119235A1

公开(公告)日：2023-04-20

申请号：US17968048

申请日：2022-10-18

Applicant: Google LLC

Inventor： Michael David Hutton ,  Georgios Konstadinidis ,  Lluis-Miquel Munguia ,  Safeen Huda ,  Gaurav Agrawal

IPC: G06F1/08 ,  G06F11/34

Abstract: A method and system for controlling performance of a workload partitioned among a plurality of accelerator chips of a multi-chip system. One or more processors may receive performance speed data for each of the accelerator chips, obtain a model of the partitioned workload, determine a portion of the workload that is either overworked or underworked based on the model of the partitioned workload and the performance speed data for each of the plurality of accelerator chips, and adjust a performance speed of an accelerator chip that performs the portion of the partitioned workload that is either overworked or underworked.

公开(公告)号：US20240036278A1

公开(公告)日：2024-02-01

申请号：US17877041

申请日：2022-07-29

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Zuowei Shen ,  Yujeong Shim ,  Teckgyu Kang ,  Jaesik Lee ,  Georgios Konstadinidis ,  Sukalpa Biswas ,  Hong Liu ,  Biao He

IPC: G02B6/42 ,  H01L23/367 ,  H01L23/473 ,  H01L25/16

CPC classification number: G02B6/4268 ,  G02B6/4274 ,  G02B6/4257 ,  H01L23/3675 ,  H01L23/473 ,  H01L25/167

Abstract: The technology generally relates to high bandwidth memory (HBM) and optical connectivity stacking. Disclosed systems and methods herein allow for 3D-stacking of HBM dies that are interconnected with an optical interface in a manner that allows for compact, high-performance computing. An optical chiplet can be configured to be placed onto a stack of HBM dies, with a cooling die that is positioned between the HBM dies and the optical chiplet. The optical chiplet may be configured to connect the HBM optics module package to one or more other components of the package via to one or more optical fibers.

公开(公告)号：US20230343768A1

公开(公告)日：2023-10-26

申请号：US17992241

申请日：2022-11-22

Applicant: Google LLC

Inventor： Horia Alexandru Toma ,  Zuowei Shen ,  Hong Liu ,  Yujeong Shim ,  Biao He ,  Jaesik Lee ,  Georgios Konstadinidis ,  Teckgyu Kang ,  Igor Arsovski ,  Sukalpa Biswas

IPC: H01L25/16

CPC classification number: H01L25/167

Abstract: The technology generally relates to disaggregating memory from an application specific integrated circuit (“ASIC”) package. For example, a high-bandwidth memory (“HBM”) optics module package may be connected to an ASIC package via one or more optical links. The HBM optics module package may include HBM dies(s), HBM chiplet(s) and an optical chiplet. The optical chiplet may be configured to connect the HBM optics module to one or more optical fibers that form an optical link with one or more other components of the ASIC package. By including an optical chiplet in the HBM optics module package, the HBM optics module package may be disaggregated from an ASIC package.

公开(公告)号：US20210286419A1

公开(公告)日：2021-09-16

申请号：US16818493

申请日：2020-03-13

Applicant: Google LLC

Inventor： Houle Gan ,  Thomas James Norrie ,  Gregory Sizikov ,  Georgios Konstadinidis

IPC: G06F1/28 ,  G06N20/00

Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.

公开(公告)号：US20230411297A1

公开(公告)日：2023-12-21

申请号：US17841188

申请日：2022-06-15

Applicant: Google LLC

Inventor： Georgios Konstadinidis ,  Woon-Seong Kwon ,  Jaesik Lee ,  Teckgyu Kang ,  Jin Y. Kim ,  Sukalpa Biswas ,  Biao He ,  Yujeong Shim

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/5384 ,  H01L23/5385 ,  H01L21/4853 ,  H01L21/486 ,  H01L25/50

Abstract: A microelectronic system may include a substrate having a first surface, one or more interposers mounted to and electrically connected to the first surface, first and second application specific integrated circuits (ASICs) each at least partially overlying and electrically connected to one of the interposers, a plurality of high-bandwidth memory elements (HBMs) each at least partially overlying and electrically connected to one of the interposers, and an active silicon bridge mounted to and electrically connected to the first surface and providing an electrical connection between the first and second ASICs, the active silicon bridge having active microelectronic devices therein. The microelectronic system may be configured such that the first and second ASICs and the active silicon bridge each have a purely digital CMOS interface therein. A plurality of bumps providing the electrical connection between the ASICs and the active silicon bridge may be configured to receive serial data therethrough.

公开(公告)号：US20230297152A1

公开(公告)日：2023-09-21

申请号：US18201974

申请日：2023-05-25

Applicant: Google LLC

Inventor： Houle Gan ,  Thomas James Norrie ,  Gregory Sizikov ,  Georgios Konstadinidis

IPC: G06F1/28 ,  G06N20/00

CPC classification number: G06F1/28 ,  G06N20/00

Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.