Invention Grant
- Patent Title: Via structures having tapered profiles for embedded interconnect bridge substrates
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Application No.: US17752717Application Date: 2022-05-24
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Publication No.: US11721631B2Publication Date: 2023-08-08
- Inventor: Jeremy D. Ecton , Hiroki Tanaka , Oscar Ojeda , Arnab Roy , Vahidreza Parichehreh , Leonel R. Arana , Chung Kwang Tan , Robert A. May
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- The original application number of the division: US15937645 2018.03.27
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48

Abstract:
Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
Public/Granted literature
- US20220285278A1 VIA STRUCTURES HAVING TAPERED PROFILES FOR EMBEDDED INTERCONNECT BRIDGE SUBSTRATES Public/Granted day:2022-09-08
Information query
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