公开(公告)号：US11373951B2

公开(公告)日：2022-06-28

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US10078204B2

公开(公告)日：2018-09-18

申请号：US14229909

申请日：2014-03-29

Applicant: Intel Corporation

Inventor： Nilanjan Z. Ghosh ,  Kevin T. McCarthy ,  Zhiyong Wang ,  Deepak Goyal ,  Changhua Liu ,  Leonel R. Arana

IPC: G01J3/28 ,  G01J3/04 ,  G01J3/44 ,  G02B21/00 ,  G01N21/65 ,  G01N21/84 ,  G01N21/95 ,  G01N21/21

CPC classification number: G02B21/008 ,  G01J3/44 ,  G01N21/21 ,  G01N21/65 ,  G01N21/8422 ,  G01N21/9501 ,  G01N2021/656 ,  G02B21/0064

Abstract: Embodiments include devices, systems and processes for using a combined confocal Raman microscope for inspecting a photo resist film material layer formed on the top surface of a layer of a substrate package, to detect border defects between regions of light exposed (e.g., cured) and unexposed (e.g., uncured) resist film material. Use of the confocal Raman microscope may provide a 3D photo-resist chemical imaging and characterization technique based on combining (1) Raman spectroscopy to identify the borders between regions of light exposed and unexposed resist along XY planes, with (2) Confocal imaging to select a Z-height of the XY planes scanned. Such detection provides fast, high resolution, non-destructive in-line inspection, and improves technical development of polymerization profiles of the resist film material.

公开(公告)号：US20220406618A1

公开(公告)日：2022-12-22

申请号：US17351537

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Leonel R. Arana ,  Jeremy D. Ecton ,  Suddhasattwa Nad ,  Brandon Christian Marin

IPC: H01L21/48 ,  H01L23/538 ,  H01L21/768

Abstract: Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

公开(公告)号：US09793233B2

公开(公告)日：2017-10-17

申请号：US15225757

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Rajasekaran Swaminathan ,  Leonel R. Arana ,  Yoshihiro Tomita ,  Yosuke Kanaoka

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L25/10 ,  H05K3/34

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

公开(公告)号：US20240203806A1

公开(公告)日：2024-06-20

申请号：US18085291

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Bai Nie ,  Leonel R. Arana ,  Dingying XU ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Jeremy D. Ecton ,  Haobo Chen ,  Bin Mu

IPC: H01L23/15 ,  C03C17/00 ,  C03C17/06 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  C03C17/004 ,  C03C17/06 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  C03C2217/253 ,  C03C2218/365

Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

公开(公告)号：US09659899B2

公开(公告)日：2017-05-23

申请号：US14796759

申请日：2015-07-10

Applicant: INTEL CORPORATION

Inventor： Sandeep B. Sane ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

公开(公告)号：US20150318258A1

公开(公告)日：2015-11-05

申请号：US14796759

申请日：2015-07-10

Applicant: INTEL CORPORATION

Inventor： SANDEEP B. SANE ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract translation: 控制模具翘曲，用于组装薄模具。 在一个示例中，半导体管芯具有背侧和与背面相对的前侧。 背面具有半导体衬底，并且前侧具有在前侧层上形成在半导体衬底上的部件。 在半导体管芯的背面形成有背面层，以在管芯被加热时抵抗管芯的翘曲，并且在管芯的前侧形成多个接触件以附着到衬底上。

公开(公告)号：US20240203853A1

公开(公告)日：2024-06-20

申请号：US18085281

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Hongxia Feng ,  Julianne Troiano ,  Dingying Xu ,  Matthew Tingey ,  Xiaoying Guo ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Bin Mu ,  Kyle Mcelhinny ,  Ashay A. Dani ,  Leonel R. Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/5384

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.

公开(公告)号：US11721631B2

公开(公告)日：2023-08-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US09808875B2

公开(公告)日：2017-11-07

申请号：US15017398

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC: B23K31/00 ,  B23K31/02 ,  B23K1/00 ,  B23K3/08 ,  B23K1/20 ,  H01L23/367

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.