Invention Grant
- Patent Title: Wafer level package structure and method of forming same
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Application No.: US17379775Application Date: 2021-07-19
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Publication No.: US11728217B2Publication Date: 2023-08-15
- Inventor: Chen-Hua Yu , Kuo-Chung Yee , Mirng-Ji Lii , Chien-Hsun Lee , Jiun Yi Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- The original application number of the division: US14144913 2013.12.31
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L25/065 ; H01L21/768 ; H01L21/56 ; H01L23/00 ; H01L25/10 ; H01L23/31 ; H01L23/538 ; H01L23/498

Abstract:
An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.
Public/Granted literature
- US20210351076A1 Wafer Level Package Structure and Method of Forming Same Public/Granted day:2021-11-11
Information query
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