Invention Grant
- Patent Title: Semiconductor package and method
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Application No.: US17373063Application Date: 2021-07-12
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Publication No.: US11728249B2Publication Date: 2023-08-15
- Inventor: Wei-Yu Chen , An-Jhih Su , Der-Chyang Yeh , Li-Hsien Huang , Ming Shih Yeh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US15907474 2018.02.28
- Main IPC: H01L23/485
- IPC: H01L23/485 ; H01L23/522 ; H01L25/10 ; H01L23/528 ; H01L23/538 ; H01L25/00 ; H01L23/31 ; H01L23/00 ; H01L23/498 ; H01L21/48 ; H01L21/56 ; H01L21/683

Abstract:
In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
Public/Granted literature
- US20210343626A1 Semiconductor Package and Method Public/Granted day:2021-11-04
Information query
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