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    Semiconductor Package and Method
    3.
    发明公开
    Semiconductor Package and Method 审中-公开

    公开(公告)号：US20240021467A1

    公开(公告)日：2024-01-18

    申请号：US18363359

    申请日：2023-08-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Wei-Yu Chen ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chien-Hsun Lee

    IPC: H01L21/768 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

    CPC classification number: H01L21/76802 ,  H01L23/5384 ,  H01L21/56 ,  H01L23/31 ,  H01L23/5386 ,  H01L2021/60022

    Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

    Chip package structure with molding layer and method for forming the same
    6.
    发明授权
    Chip package structure with molding layer and method for forming the same 有权

    公开(公告)号：US11469215B2

    公开(公告)日：2022-10-11

    申请号：US16801395

    申请日：2020-02-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Yu Chen ,  An-Jhih Su

    IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/03 ,  H01L23/498 ,  H01L23/31

    Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.

    Semiconductor Structure and Method
    7.
    发明申请
    Semiconductor Structure and Method 有权

    公开(公告)号：US20220028823A1

    公开(公告)日：2022-01-27

    申请号：US16935465

    申请日：2020-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Shen Cheng ,  Wei-Yu Chen ,  Philip Yu-Shuan Chung ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu

    IPC: H01L23/00

    Abstract: A method for bonding semiconductor substrates includes placing a die on a substrate and performing a heating process on the die and the substrate to bond the respective first connectors with the respective second connectors. Respective first connectors of a plurality of first connectors on the die contact respective second connectors of a plurality of second connectors on the substrate. The heating process includes placing a mask between a laser generator and the substrate and performing a laser shot. The mask includes a masking layer and a transparent layer. Portions of the masking layer are opaque. The laser passes through a first gap in the masking layer and through the transparent layer to heat a first portion of a top side of the die opposite the substrate.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210066263A1

    公开(公告)日：2021-03-04

    申请号：US16795523

    申请日：2020-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Ming-Shih Yeh

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00

    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

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