Invention Grant
- Patent Title: Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same
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Application No.: US17717296Application Date: 2022-04-11
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Publication No.: US11742349B2Publication Date: 2023-08-29
- Inventor: Ta-Chun Lin , Kuo-Hua Pan , Jhon Jhy Liaw , Shien-Yang Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- The original application number of the division: US16745107 2020.01.16
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/088 ; H01L29/78 ; H01L29/66 ; H01L21/8234 ; H01L29/06
Abstract:
A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.
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