公开(公告)号：US12051695B2

公开(公告)日：2024-07-30

申请号：US18360166

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

公开(公告)号：US11302692B2

公开(公告)日：2022-04-12

申请号：US16745107

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20230387114A1

公开(公告)日：2023-11-30

申请号：US18360166

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462

Abstract: A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

公开(公告)号：US20210225839A1

公开(公告)日：2021-07-22

申请号：US16745107

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20240355896A1

公开(公告)日：2024-10-24

申请号：US18760602

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US12057485B2

公开(公告)日：2024-08-06

申请号：US17409086

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L21/027

CPC classification number: H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US11742349B2

公开(公告)日：2023-08-29

申请号：US17717296

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

公开(公告)号：US20220238519A1

公开(公告)日：2022-07-28

申请号：US17717296

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

公开(公告)号：US20210384311A1

公开(公告)日：2021-12-09

申请号：US17409086

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L29/40 ,  H01L29/165

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.