Invention Grant
- Patent Title: Integrated circuitry and method used in forming a memory array comprising strings of memory cells
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Application No.: US17030751Application Date: 2020-09-24
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Publication No.: US11744069B2Publication Date: 2023-08-29
- Inventor: John D. Hopkins , Alyssa N. Scarbrough
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H10B43/27 ; H01L21/311 ; H10B43/10

Abstract:
Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier. The immediately-adjacent tier comprises material that is of different composition from that of the lowest insulator tier. Other embodiments, including methods, are disclosed.
Public/Granted literature
- US20220068958A1 Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells Public/Granted day:2022-03-03
Information query
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