An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.