公开(公告)号：US11804266B2

公开(公告)日：2023-10-31

申请号：US17992143

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwoo Lee ,  Sangjoon Kim ,  Yongmin Ju

IPC: G11C11/54 ,  G11C13/00 ,  G06N3/063

CPC classification number: G11C13/0069 ,  G06N3/063 ,  G11C11/54 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0061

Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

公开(公告)号：US11581042B2

公开(公告)日：2023-02-14

申请号：US17181259

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwoo Lee ,  Sangjoon Kim ,  Seungchul Jung ,  Yongmin Ju

IPC: G11C13/00 ,  G06F7/544 ,  G06N3/063

Abstract: Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit.

公开(公告)号：US11756610B2

公开(公告)日：2023-09-12

申请号：US17974852

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongmin Ju ,  Sangjoon Kim ,  Hyungwoo Lee ,  Seungchul Jung

IPC: G11C7/12 ,  G11C11/54 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10 ,  G11C27/02

CPC classification number: G11C11/54 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/1006 ,  G11C27/02

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

公开(公告)号：US11587616B2

公开(公告)日：2023-02-21

申请号：US17141474

申请日：2021-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwoo Lee ,  Sangjoon Kim ,  Yongmin Ju

IPC: G11C11/54 ,  G11C13/00 ,  G06N3/063

Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

公开(公告)号：US11514980B2

公开(公告)日：2022-11-29

申请号：US17150891

申请日：2021-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongmin Ju ,  Sangjoon Kim ,  Hyungwoo Lee ,  Seungchul Jung

IPC: G11C7/12 ,  G11C11/54 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C27/02 ,  G11C7/10

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.