- 专利标题: Dual trace thickness for single layer routing
-
申请号: US16017671申请日: 2018-06-25
-
公开(公告)号: US11769719B2公开(公告)日: 2023-09-26
- 发明人: Jonathan Rosch , Wei-Lun Jen , Cheng Xu , Liwei Cheng , Andrew Brown , Yikang Deng
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt. P.C.
- 主分类号: H05K1/11
- IPC分类号: H05K1/11 ; H05K1/18 ; H01L23/498 ; H01L21/48 ; H05K1/02
摘要:
Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.
公开/授权文献
- US20190393143A1 DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING 公开/授权日:2019-12-26
信息查询