公开(公告)号：US11276618B2

公开(公告)日：2022-03-15

申请号：US15967122

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Andrew J. Brown

IPC: H01L23/14 ,  B32B27/12 ,  B32B5/02 ,  B32B5/26 ,  B32B27/38 ,  B32B27/36 ,  H01L23/538 ,  H01L21/48 ,  H05K1/03 ,  H01L23/498 ,  H05K5/00 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US11495555B2

公开(公告)日：2022-11-08

申请号：US15921511

申请日：2018-03-14

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Jonathan Rosch ,  Andrew Brown ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/498 ,  H01F27/40 ,  H01L21/48

Abstract: Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.

公开(公告)号：US20190206774A1

公开(公告)日：2019-07-04

申请号：US15858650

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Jonathan Rosch

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H05K1/02 ,  H05K3/00 ,  H05K1/14

Abstract: A multi-layer solder-resist provides useful adhesion to a semiconductor device package substrate while allowing for increasingly small geometries of bond pads and spacings.

公开(公告)号：US11769719B2

公开(公告)日：2023-09-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Wei-Lun Jen ,  Cheng Xu ,  Liwei Cheng ,  Andrew Brown ,  Yikang Deng

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/111 ,  H05K1/115 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20190333832A1

公开(公告)日：2019-10-31

申请号：US15967122

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Andrew J. Brown

IPC: H01L23/14 ,  B32B27/12 ,  B32B5/02 ,  B32B5/26 ,  B32B27/38 ,  B32B27/36 ,  H01L23/538 ,  H01L21/48

Abstract: An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.