Invention Grant
- Patent Title: Apparatuses exhibiting enhanced stress resistance and planarity, and related microelectronic devices and memory devices
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Application No.: US17339560Application Date: 2021-06-04
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Publication No.: US11769738B2Publication Date: 2023-09-26
- Inventor: Kyle K. Kirby , Chao Wen Wang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- The original application number of the division: US16554986 2019.08.29
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/528 ; H01L23/31 ; H01L23/29 ; H01L25/065 ; H01L21/74 ; H01L21/56 ; H01L21/48 ; H01L23/492 ; H01L23/532 ; H01L23/538

Abstract:
An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.
Public/Granted literature
Information query
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