公开(公告)号：US11264388B2

公开(公告)日：2022-03-01

申请号：US16876362

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L27/108 ,  H01L23/528 ,  G11C5/10 ,  H01L49/02 ,  G11C5/02 ,  H01L23/522

Abstract: A microelectronic device comprises a die comprising a front side and a back side opposite the front side, one or more components of integrated circuitry within a base material of the die and between the front side and the back side of the die, and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors comprise a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further comprises a first conductive via comprising a conductive material extending through the base material, the first conductive via in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device. Related apparatuses including a decoupling capacitor in a back side, and related electronic systems and methods are also described.

公开(公告)号：US12176312B2

公开(公告)日：2024-12-24

申请号：US18402426

申请日：2024-01-02

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L21/00 ,  H01L23/00

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US20240136315A1

公开(公告)日：2024-04-25

申请号：US18402426

申请日：2024-01-02

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/11011 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11912

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US11769738B2

公开(公告)日：2023-09-26

申请号：US17339560

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Chao Wen Wang

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L25/065 ,  H01L21/74 ,  H01L21/56 ,  H01L21/48 ,  H01L23/492 ,  H01L23/532 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/743 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/4924 ,  H01L23/528 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/53214 ,  H01L23/53228 ,  H01L25/0657 ,  H01L2225/06513

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

公开(公告)号：US11894329B2

公开(公告)日：2024-02-06

申请号：US17809224

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/11011 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11912

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US20220328442A1

公开(公告)日：2022-10-13

申请号：US17809224

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L23/00

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US20210358915A1

公开(公告)日：2021-11-18

申请号：US16876362

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  G11C5/02 ,  G11C5/10

Abstract: A microelectronic device comprises a die comprising a front side and a back side opposite the front side, one or more components of integrated circuitry within a base material of the die and between the front side and the back side of the die, and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors comprise a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further comprises a first conductive via comprising a conductive material extending through the base material, the first conductive via in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device. Related apparatuses including a decoupling capacitor in a back side, and related electronic systems and methods are also described.

公开(公告)号：US20210407958A1

公开(公告)日：2021-12-30

申请号：US16912547

申请日：2020-06-25

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L23/00 ,  B23K1/00 ,  B23K1/005

Abstract: A radiative heat collective bonder or gangbonder for packaging a semiconductor die stack is provided. The bonder generally includes a shroud positioned at least partially around the die stack and a radiative heat source positioned inward of the shroud and configured to emit a radiative heat flux in a direction away from the shroud. The bonder may further include a bondhead configured to contact the backside of the topmost die in the die stack and optionally include another bondhead configured to contact a substrate beneath the die stack. The radiative heat source may be configured to direct the radiative heat flux to at least a portion of the die stack to reduce a vertical temperature gradient in the die stack. One or both of the bondheads may be configured to concurrently direct a conductive heat flux into the die stack.

公开(公告)号：US20210296289A1

公开(公告)日：2021-09-23

申请号：US17339560

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Chao Wen Wang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/532

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

公开(公告)号：US20210066207A1

公开(公告)日：2021-03-04

申请号：US16554986

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Chao Wen Wang

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L23/492 ,  H01L25/065 ,  H01L21/74 ,  H01L21/56 ,  H01L21/48

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.