Invention Grant
- Patent Title: Semiconductor device with reduced loading effect
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Application No.: US17652761Application Date: 2022-02-28
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Publication No.: US11776850B2Publication Date: 2023-10-03
- Inventor: Wei-Lun Chen , Li-Te Lin , Chao-Hsien Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/3065 ; H01L21/308 ; H01L27/088 ; H01L29/06 ; H01L29/10 ; H01L21/311 ; H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L29/78

Abstract:
The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
Public/Granted literature
- US20220181212A1 SEMICONDUCTOR DEVICE WITH REDUCED LOADING EFFECT Public/Granted day:2022-06-09
Information query
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