Invention Grant
- Patent Title: Memory device having 2-transistor vertical memory cell and a common plate
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Application No.: US17003065Application Date: 2020-08-26
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Publication No.: US11776907B2Publication Date: 2023-10-03
- Inventor: Kamal M. Karda , Karthik Sarpatwari , Haitao Liu , Durai Vishak Nirmal Ramaswamy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L29/24 ; G11C5/06 ; H10B12/00

Abstract:
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.
Public/Granted literature
- US20210066196A1 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE Public/Granted day:2021-03-04
Information query
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