- 专利标题： Semiconductor device having buried logic conductor type of complementary field effect transistor, method of forming same
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申请号： US17840430申请日： 2022-06-14
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公开(公告)号： US11776958B2公开(公告)日： 2023-10-03
- 发明人: Guo-Huei Wu , Pochun Wang , Chih-Liang Chen , Li-Chun Tien
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Hauptman Ham, LLP
- 主分类号： H01L27/092
- IPC分类号： H01L27/092 ; G06F30/392 ; G06F30/31 ; H01L21/8238 ; H01L23/522 ; H01L23/528 ; G06F111/02
摘要：
A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.
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