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公开(公告)号：US12079559B2
公开(公告)日：2024-09-03
申请号：US18362889
申请日：2023-07-31
IPC分类号： G06F30/392 , G03F1/36 , G03F7/00 , G06F30/398
CPC分类号： G06F30/392 , G03F1/36 , G03F7/70441 , G06F30/398
摘要： A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.
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公开(公告)号：US12027461B2
公开(公告)日：2024-07-02
申请号：US17108752
申请日：2020-12-01
发明人： Chih-Liang Chen , Guo-Huei Wu , Li-Chun Tien
IPC分类号： H01L23/528 , G06F30/392 , G06F30/3953 , G06F119/06
CPC分类号： H01L23/5286 , G06F30/392 , G06F30/3953 , G06F2119/06
摘要： A semiconductor device, includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as a ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.
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公开(公告)号：US11894383B2
公开(公告)日：2024-02-06
申请号：US17829330
申请日：2022-05-31
发明人： Pochun Wang , Guo-Huei Wu , Hui-Zhong Zhuang , Chih-Liang Chen , Li-Chun Tien
IPC分类号： H01L27/12 , H01L21/84 , H01L23/522 , H01L23/528 , B82Y10/00 , H01L21/822 , H01L21/8238 , H01L29/66 , H01L29/775 , H01L21/768 , H01L27/02 , H01L27/06 , H01L27/092 , H01L29/423 , H01L29/786 , H01L21/74 , H01L27/088 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/845 , H01L23/528 , H01L23/5226
摘要： A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
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公开(公告)号：US11783109B2
公开(公告)日：2023-10-10
申请号：US17395148
申请日：2021-08-05
IPC分类号： G06F30/392 , G03F7/20 , G03F1/36 , G06F30/398 , G03F7/00
CPC分类号： G06F30/392 , G03F1/36 , G03F7/70441 , G06F30/398
摘要： A method of forming an IC device includes creating a recess by removing at least a portion of a channel of a first transistor and a portion of a gate electrode, the gate electrode being common to the first transistor and an underlying second transistor. The method includes filling the recess with a dielectric material to form an isolation layer, and constructing a slot via overlying the isolation layer.
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公开(公告)号：US11776958B2
公开(公告)日：2023-10-03
申请号：US17840430
申请日：2022-06-14
发明人： Guo-Huei Wu , Pochun Wang , Chih-Liang Chen , Li-Chun Tien
IPC分类号： H01L27/092 , G06F30/392 , G06F30/31 , H01L21/8238 , H01L23/522 , H01L23/528 , G06F111/02
CPC分类号： H01L27/0922 , G06F30/31 , G06F30/392 , H01L21/823871 , H01L23/5226 , H01L23/5286 , G06F2111/02
摘要： A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.
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公开(公告)号：US11004855B2
公开(公告)日：2021-05-11
申请号：US16515709
申请日：2019-07-18
发明人： Pochun Wang , Ting-Wei Chiang , Chih-Ming Lai , Hui-Zhong Zhuang , Jung-Chan Yang , Ru-Gun Liu , Shih-Ming Chang , Ya-Chi Chou , Yi-Hsiung Lin , Yu-Xuan Huang , Guo-Huei Wu , Yu-Jung Chang
IPC分类号： H01L27/108 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/02
摘要： An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
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公开(公告)号：US20190067290A1
公开(公告)日：2019-02-28
申请号：US15691974
申请日：2017-08-31
发明人： Pochun Wang , Ting-Wei Chiang , Chih-Ming Lai , Hui-Zhong Zhuang , Jung-Chan Yang , Ru-Gun Liu , Shih-Ming Chang , Ya-Chi Chou , Yi-Hsiung Lin , Yu-Xuan Huang , Yu-Jung Chang , Guo-Huei Wu
IPC分类号： H01L27/108 , H01L21/768 , H01L23/522 , H01L27/02 , H01L23/528
CPC分类号： H01L27/10823 , H01L21/76897 , H01L23/522 , H01L23/528 , H01L27/0207 , H01L27/10808 , H01L27/10826 , H01L27/10829
摘要： An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
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公开(公告)号：US12033935B2
公开(公告)日：2024-07-09
申请号：US17836896
申请日：2022-06-09
发明人： Guo-Huei Wu , Hui-Zhong Zhuang , Chih-Liang Chen , Cheng-Chi Chuang , Shang-Wen Chang , Yi-Hsun Chiu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L23/5283
摘要： A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
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公开(公告)号：US20240222269A1
公开(公告)日：2024-07-04
申请号：US18604071
申请日：2024-03-13
发明人： Guo-Huei Wu , Hui-Zhong Zhuang , Chih-Liang Chen , Cheng-Chi Chuang , Shang-Wen Chang , Yi-Hsun Chiu
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L23/5283
摘要： A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
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公开(公告)号：US12027598B2
公开(公告)日：2024-07-02
申请号：US17331356
申请日：2021-05-26
发明人： Guo-Huei Wu , Pochun Wang , Chih-Liang Chen , Li-Chun Tien
IPC分类号： H01L29/423 , H01L29/06
CPC分类号： H01L29/42392 , H01L29/0649 , H01L29/0673
摘要： A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.
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