Invention Grant
- Patent Title: Gate-all-around device
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Application No.: US17582731Application Date: 2022-01-24
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Publication No.: US11776998B2Publication Date: 2023-10-03
- Inventor: Chung-En Tsai , Chia-Che Chung , Chee-Wee Liu , Fang-Liang Lu , Yu-Shiang Huang , Hung-Yu Yeh , Chien-Te Tu , Yi-Chun Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. , NATIONAL TAIWAN UNIVERSITY
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,NATIONAL TAIWAN UNIVERSITY
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,NATIONAL TAIWAN UNIVERSITY
- Current Assignee Address: TW Hsinchu; TW Taipei
- Agency: Maschoff Brennan
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/02 ; H01L21/306 ; H01L29/08 ; H01L29/10 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/786

Abstract:
A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.
Public/Granted literature
- US20220149172A1 GATE-ALL-AROUND DEVICE Public/Granted day:2022-05-12
Information query
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