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公开(公告)号:US10777663B2
公开(公告)日:2020-09-15
申请号:US16150182
申请日:2018-10-02
发明人: Chung-En Tsai , Fang-Liang Lu , Pin-Shiang Chen , Chee-Wee Liu
IPC分类号: H01L29/66 , H01L29/167 , H01L21/223 , H01L21/3065 , H01L29/78 , H01L29/45 , H01L21/3105 , H01L21/02 , H01L29/165 , H01L29/08
摘要: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.
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公开(公告)号:US10340383B2
公开(公告)日:2019-07-02
申请号:US15277079
申请日:2016-09-27
发明人: Huang-Siang Lan , CheeWee Liu , Chi-Wen Liu , Shih-Hsien Huang , I-Hsieh Wong , Hung-Yu Yeh , Chung-En Tsai
IPC分类号: H01L29/78 , H01L29/08 , H01L29/10 , H01L29/165 , H01L27/092 , H01L21/02 , H01L21/8238 , H01L29/66
摘要: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
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公开(公告)号:US11631768B2
公开(公告)日:2023-04-18
申请号:US16459511
申请日:2019-07-01
发明人: Huang-Siang Lan , CheeWee Liu , Chi-Wen Liu , Shih-Hsien Huang , I-Hsieh Wong , Hung-Yu Yeh , Chung-En Tsai
IPC分类号: H01L29/78 , H01L29/08 , H01L29/10 , H01L29/165 , H01L27/092 , H01L21/02 , H01L29/66 , H01L21/8238
摘要: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
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公开(公告)号:US11374115B2
公开(公告)日:2022-06-28
申请号:US17019007
申请日:2020-09-11
发明人: Chung-En Tsai , Fang-Liang Lu , Pin-Shiang Chen , Chee-Wee Liu
IPC分类号: H01L29/66 , H01L29/167 , H01L21/223 , H01L21/3065 , H01L29/78 , H01L29/45 , H01L21/3105 , H01L21/02 , H01L29/165 , H01L29/08
摘要: A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.
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公开(公告)号:US11244945B2
公开(公告)日:2022-02-08
申请号:US16548730
申请日:2019-08-22
发明人: Chih-Hsiung Huang , Chung-En Tsai , Chee-Wee Liu , Kun-Wa Kuok , Yi-Hsiu Hsiao
IPC分类号: H01L27/092 , H01L29/49 , H01L29/66 , H01L21/28 , H01L21/8238 , H01L29/40
摘要: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.
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公开(公告)号:US11233120B2
公开(公告)日:2022-01-25
申请号:US16850974
申请日:2020-04-16
发明人: Chung-En Tsai , Chia-Che Chung , Chee-Wee Liu , Fang-Liang Lu , Yu-Shiang Huang , Hung-Yu Yeh , Chien-Te Tu , Yi-Chun Liu
IPC分类号: H01L29/06 , H01L29/66 , H01L21/306 , H01L29/78 , H01L29/08 , H01L21/02 , H01L29/423 , H01L29/10
摘要: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.
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公开(公告)号:US10957784B2
公开(公告)日:2021-03-23
申请号:US16450637
申请日:2019-06-24
发明人: I-Hsieh Wong , Samuel C. Pan , Chee-Wee Liu , Huang-Siang Lan , Chung-En Tsai , Fang-Liang Lu
IPC分类号: H01L29/66 , H01L21/306 , H01L21/268 , H01L21/02 , H01L29/08 , H01L21/324 , H01L29/423 , H01L29/06 , H01L29/78 , H01L29/165 , H01L29/775 , H01L29/786 , B82Y10/00 , H01L29/40 , H01L29/10 , H01L21/265 , H01L21/762
摘要: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
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公开(公告)号:US10332985B2
公开(公告)日:2019-06-25
申请号:US15940423
申请日:2018-03-29
发明人: I-Hsieh Wong , Samuel C. Pan , Chee-Wee Liu , Huang-Siang Lan , Chung-En Tsai , Fang-Liang Lu
IPC分类号: H01L21/336 , H01L29/66 , H01L21/306 , H01L21/268 , H01L21/02 , H01L29/08 , H01L21/324 , H01L29/423 , H01L29/06 , H01L29/78 , H01L29/165 , H01L29/10 , H01L21/265 , H01L21/762
摘要: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
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公开(公告)号:US11600703B2
公开(公告)日:2023-03-07
申请号:US17162896
申请日:2021-01-29
发明人: Shahaji B. More , Cheng-Han Lee , Shih-Chieh Chang , Shih-Ya Lin , Chung-En Tsai , Chee-Wee Liu
IPC分类号: H01L29/161 , H01L29/786 , H01L29/423 , H01L29/66 , H01L29/40
摘要: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.
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公开(公告)号:US20220246726A1
公开(公告)日:2022-08-04
申请号:US17162896
申请日:2021-01-29
发明人: Shahaji B. MORE , Cheng-Han Lee , Shih-Chieh Chang , Shih-Ya Lin , Chung-En Tsai , Chee-Wee Liu
IPC分类号: H01L29/161 , H01L29/786 , H01L29/423 , H01L29/66 , H01L29/40
摘要: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.
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