Invention Grant
- Patent Title: Method of forming electronic chip package having a conductive layer between a chip and a support
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Application No.: US17491189Application Date: 2021-09-30
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Publication No.: US11784104B2Publication Date: 2023-10-10
- Inventor: Olivier Ory , Romain Jaillet
- Applicant: STMICROELECTRONICS (TOURS) SAS
- Applicant Address: FR Tours
- Assignee: STMICROELECTRONICS (TOURS) SAS
- Current Assignee: STMICROELECTRONICS (TOURS) SAS
- Current Assignee Address: FR Tours
- Agency: SEED INTELLECTUAL PROPERTY LAW GROUP LLP
- Priority: FR 57899 2018.09.03
- The original application number of the division: US16552464 2019.08.27
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31 ; H01L21/78 ; H01L29/861
Abstract:
The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.
Public/Granted literature
- US20220020652A1 ELECTRONIC CHIP PACKAGE HAVING A SUPPORT AND A CONDUCTIVE LAYER ON THE SUPPORT Public/Granted day:2022-01-20
Information query
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