- 专利标题: System for generating layout diagram including wiring arrangement
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申请号: US17885106申请日: 2022-08-10
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公开(公告)号: US11790151B2公开(公告)日: 2023-10-17
- 发明人: Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Hauptman Ham, LLP
- 分案原申请号: US16299973 2019.03.12
- 主分类号: G06F30/398
- IPC分类号: G06F30/398 ; G06F30/392 ; G06F30/394 ; G06F119/18
摘要:
A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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