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公开(公告)号：US11983475B2
公开(公告)日：2024-05-14
申请号：US18165411
申请日：2023-02-07
发明人： Pin-Dai Sue , Po-Hsiang Huang , Fong-Yuan Chang , Chi-Yu Lu , Sheng-Hsiung Chen , Chin-Chou Liu , Lee-Chung Lu , Yen-Hung Lin , Li-Chun Tien , Yi-Kan Cheng
IPC分类号： G06F30/00 , G06F30/373 , G06F30/392 , G06F30/394 , G06F111/20
CPC分类号： G06F30/392 , G06F30/373 , G06F30/394 , G06F2111/20
摘要： A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
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2.发明公开公开(公告)号：US20240120639A1
公开(公告)日：2024-04-11
申请号：US18448045
申请日：2023-08-10
发明人： Po-Hsiang Huang , Fong-Yuan Chang , Tsui-Ping Wang , Yi-Shin Chu
CPC分类号： H01Q1/2283 , H01L23/66 , H01Q1/50 , H01Q23/00
摘要： A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
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公开(公告)号：US11790151B2
公开(公告)日：2023-10-17
申请号：US17885106
申请日：2022-08-10
发明人： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
摘要： A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US11755798B2
公开(公告)日：2023-09-12
申请号：US17340662
申请日：2021-06-07
发明人： Chi-Lin Liu , Jerry Chang-Jui Kao , Wei-Hsiang Ma , Lee-Chung Lu , Fong-Yuan Chang , Sheng-Hsiung Chen , Shang-Chih Hsieh
IPC分类号： G06F30/327 , G06F111/06 , G06F119/18
CPC分类号： G06F30/327 , G06F2111/06 , G06F2119/18
摘要： A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.
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公开(公告)号：US11281836B2
公开(公告)日：2022-03-22
申请号：US17222021
申请日：2021-04-05
发明人： Fong-Yuan Chang , Jyun-Hao Chang , Sheng-Hsiung Chen , Ho Che Yu , Lee-Chung Lu , Ni-Wan Fan , Po-Hsiang Huang , Chi-Yu Lu , Jeo-Yen Lee
IPC分类号： G06F30/392 , H01L27/118 , G06F30/398 , G06F30/39 , H01L23/538 , H01L27/02
摘要： A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.
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公开(公告)号：US11043473B2
公开(公告)日：2021-06-22
申请号：US16718352
申请日：2019-12-18
发明人： Chih-Lin Chen , Chin-Chou Liu , Fong-Yuan Chang , Hui-Yu Lee , Po-Hsiang Huang
IPC分类号： H01L23/12 , H01L23/34 , H01L25/065 , H01L49/02 , H01L23/48 , H01L23/522 , H01L23/00 , H01L21/768 , H01L25/00 , H01L23/538 , H01L23/528
摘要： An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.
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公开(公告)号：US11030366B2
公开(公告)日：2021-06-08
申请号：US15930010
申请日：2020-05-12
发明人： Chi-Lin Liu , Sheng-Hsiung Chen , Jerry Chang-Jui Kao , Fong-Yuan Chang , Lee-Chung Lu , Shang-Chih Hsieh , Wei-Hsiang Ma
IPC分类号： G06F30/327 , G06F111/06 , G06F119/18
摘要： A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram; and selecting one group (selected group) of the recurrent ad hoc groups such that: the cells in the selected group have connections representing a corresponding logic circuit; each cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of a corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.
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公开(公告)号：US20200043832A1
公开(公告)日：2020-02-06
申请号：US16516966
申请日：2019-07-19
IPC分类号： H01L23/48 , H01L21/822 , H01L23/00 , H01L25/065
摘要： A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
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公开(公告)号：US10552568B2
公开(公告)日：2020-02-04
申请号：US15845101
申请日：2017-12-18
发明人： Sheng-Hsiung Chen , Jyun-Hao Chang , Ting-Wei Chiang , Fong-Yuan Chang , I-Lun Tseng , Po-Hsiang Huang
IPC分类号： G06F17/50
摘要： A method of modifying a cell includes identifying a maximum overlapped pin group. The method further includes determining a number of pins in the maximum overlapped pin group. The method further includes determining a span region of the maximum overlapped pin group. The method further includes comparing the number of pins and the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold. The method further includes fabricating a mask based on the increased length of the at least one pin.
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公开(公告)号：US10402534B2
公开(公告)日：2019-09-03
申请号：US15878009
申请日：2018-01-23
摘要： A method of generating a layout of an IC includes identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell, and determining whether or not the target pin is capable of being extended into the second cell. Based on a determination that the target pin is capable of being extended into the second cell, the target pin is modified to include an extension into the second cell, the target pin thereby crossing the shared boundary. At least one of the identifying, determining, or modifying is executed by a processor of a computer.
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