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公开(公告)号：US11790151B2
公开(公告)日：2023-10-17
申请号：US17885106
申请日：2022-08-10
发明人： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
摘要： A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US11556691B2
公开(公告)日：2023-01-17
申请号：US16573698
申请日：2019-09-17
发明人： Wei-Yi Hu , Chih-Ming Chao , Jung-Chou Tsai
IPC分类号： G06F30/398 , G03F1/36 , G06F30/392
摘要： Disclosed are methods for designing semiconductor devices, conductive layer patterns, and interconnection layer patterns including the operations of analyzing an initial semiconductor design layout to identify excessive open spaces between adjacent conductive elements or lines within an interconnection layer pattern, selecting or generating a dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout that incorporates the dummy pattern into first interconnection layer pattern to reduce the open space.
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公开(公告)号：US11532580B2
公开(公告)日：2022-12-20
申请号：US16883929
申请日：2020-05-26
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522 , H01L25/065
摘要： An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.
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公开(公告)号：US12002776B2
公开(公告)日：2024-06-04
申请号：US17811896
申请日：2022-07-12
IPC分类号： H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065
CPC分类号： H01L24/06 , H01L23/5226 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/50 , H01L24/89 , H01L25/0655 , H01L2224/0557 , H01L2224/06131 , H01L2224/08225 , H01L2224/80895 , H01L2224/80896
摘要： An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.
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公开(公告)号：US11775727B2
公开(公告)日：2023-10-03
申请号：US16299973
申请日：2019-03-12
发明人： Fong-Yuan Chang , Chin-Chou Liu , Hui-Zhong Zhuang , Meng-Kai Hsu , Pin-Dai Sue , Po-Hsiang Huang , Yi-Kan Cheng , Chi-Yu Lu , Jung-Chou Tsai
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F119/18
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
摘要： A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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