Invention Grant
- Patent Title: Integrated capacitor with sidewall having reduced roughness
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Application No.: US17156793Application Date: 2021-01-25
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Publication No.: US11798979B2Publication Date: 2023-10-24
- Inventor: Elizabeth Costner Stewart , Jeffrey A. West , Thomas D. Bonifield , Joseph Andre Gallegos , Jay Sung Chun , Zhiyi Yu
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Frank D. Cimino
- The original application number of the division: US15348580 2016.11.10
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L21/02 ; H01L21/768 ; H01L21/311

Abstract:
An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.
Public/Granted literature
- US20210143249A1 INTEGRATED CAPACITOR WITH SIDEWALL HAVING REDUCED ROUGHNESS Public/Granted day:2021-05-13
Information query
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