公开(公告)号：US20240112953A1

公开(公告)日：2024-04-04

申请号：US18148231

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Kashyap Barot ,  Viresh Chinchansure ,  Sreeram N S

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.

公开(公告)号：US20230197634A1

公开(公告)日：2023-06-22

申请号：US17558017

申请日：2021-12-21

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L28/10

Abstract: An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 μm to 5.0 μm, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 μm, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.

公开(公告)号：US10978548B2

公开(公告)日：2021-04-13

申请号：US15348580

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Jeffrey A. West ,  Thomas D. Bonifield ,  Joseph Andre Gallegos ,  Jay Sung Chun ,  Zhiyi Yu

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/311

Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.

公开(公告)号：US12230669B2

公开(公告)日：2025-02-18

申请号：US18242717

申请日：2023-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L23/522 ,  H01L27/02 ,  H01L49/02

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US20230282595A1

公开(公告)日：2023-09-07

申请号：US17833380

申请日：2022-06-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L2223/5446

Abstract: An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.

公开(公告)号：US11532693B2

公开(公告)日：2022-12-20

申请号：US17152230

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifeld

IPC: H01L23/552 ,  H01L23/49 ,  H01L23/522 ,  H01L49/02

Abstract: Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

公开(公告)号：US20160300693A1

公开(公告)日：2016-10-13

申请号：US14682651

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Neng Jiang ,  Elizabeth Costner Stewart ,  Nicholas S. Dellas

IPC: H01J37/32 ,  H03H3/02

CPC classification number: H03H3/02 ,  H03H2003/025

Abstract: A method of fabricating a sloped termination of a molybdenum layer includes providing the molybdenum layer and applying a photo resist material to the molybdenum layer. The photo resist material is exposed under a defocus condition to generate a resist mask having an edge portion. The molybdenum layer is etched at least at the edge portion of the resist mask to result in a sloped termination of the molybdenum layer.

Abstract translation: 制造钼层的倾斜终端的方法包括提供钼层并将光抗蚀剂材料施加到钼层。 光抗蚀剂材料在散焦条件下曝光以产生具有边缘部分的抗蚀剂掩模。 至少在抗蚀剂掩模的边缘部分处蚀刻钼层，导致钼层的倾斜终止。

公开(公告)号：US20240120367A1

公开(公告)日：2024-04-11

申请号：US18390395

申请日：2023-12-20

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01G4/30 ,  H01L23/00 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US20230056046A1

公开(公告)日：2023-02-23

申请号：US17682762

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Byron Lovell Williams ,  Elizabeth Costner Stewart ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.

公开(公告)号：US11049820B2

公开(公告)日：2021-06-29

申请号：US16049256

申请日：2018-07-30

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Jeffrey A. West

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L23/31

Abstract: An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.