Invention Grant
- Patent Title: Multi-level cache coherency protocol for cache line evictions
-
Application No.: US17130905Application Date: 2020-12-22
-
Publication No.: US11803470B2Publication Date: 2023-10-31
- Inventor: Amit Apte , Ganesh Balakrishnan , Ann Ling , Vydhyanathan Kalyanasundharam
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: FIG. 1 Patents
- Main IPC: G06F12/0817
- IPC: G06F12/0817
Abstract:
Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.
Public/Granted literature
- US20220100661A1 MULTI-LEVEL CACHE COHERENCY PROTOCOL FOR CACHE LINE EVICTIONS Public/Granted day:2022-03-31
Information query
IPC分类:
