公开(公告)号：US20240232084A9

公开(公告)日：2024-07-11

申请号：US17957823

申请日：2022-10-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Balakrishnan ,  Amit Apte ,  Ann Ling ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.

公开(公告)号：US20240111683A1

公开(公告)日：2024-04-04

申请号：US17958179

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan

IPC: G06F12/0895

CPC classification number: G06F12/0895 ,  G06F2212/60

Abstract: A method includes, in a cache directory, storing a set of entries corresponding to one or more memory regions having a first region size when the cache directory is in a first configuration, and based on a workload sparsity metric, reconfiguring the cache directory to a second configuration. In the second configuration, each entry in the set of entries corresponds to a memory region having a second region size.

公开(公告)号：US11507517B2

公开(公告)日：2022-11-22

申请号：US17033212

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan

IPC: G06F12/0895

Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

公开(公告)号：US11954033B1

公开(公告)日：2024-04-09

申请号：US17957823

申请日：2022-10-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Balakrishnan ,  Amit Apte ,  Ann Ling ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.

公开(公告)号：US11803470B2

公开(公告)日：2023-10-31

申请号：US17130905

申请日：2020-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan ,  Ann Ling ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.

公开(公告)号：US20240134795A1

公开(公告)日：2024-04-25

申请号：US17957823

申请日：2022-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Balakrishnan ,  Amit Apte ,  Ann Ling ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.

公开(公告)号：US20220100672A1

公开(公告)日：2022-03-31

申请号：US17033212

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan

IPC: G06F12/0895

Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

公开(公告)号：US20220100661A1

公开(公告)日：2022-03-31

申请号：US17130905

申请日：2020-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan ,  Ann Ling ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0817

Abstract: Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.