- Patent Title: Analog error detection and correction in analog in-memory crossbars
-
Application No.: US17580146Application Date: 2022-01-20
-
Publication No.: US11804859B2Publication Date: 2023-10-31
- Inventor: John Paul Strachan , Can Li , Catherine Graves
- Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Applicant Address: US TX Houston
- Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee Address: US TX Spring
- Agency: Sheppard Mullin Richter & Hampton LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/15 ; G11C13/00 ; H03M13/11 ; G11C27/00

Abstract:
An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.
Public/Granted literature
- US20230246655A1 ANALOG ERROR DETECTION AND CORRECTION IN ANALOG IN-MEMORY CROSSBARS Public/Granted day:2023-08-03
Information query
IPC分类: