Invention Grant
- Patent Title: History-based selective cache line invalidation requests
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Application No.: US17514811Application Date: 2021-10-29
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Publication No.: US11822479B2Publication Date: 2023-11-21
- Inventor: Paul J. Moyer
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Volpe Koenig
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0891

Abstract:
Techniques for performing cache operations are provided. The techniques include recording an indication that providing exclusive access of a first cache line to a first processor is deemed problematic; detecting speculative execution of a store instruction by the first processor to the first cache line; and in response to the detecting, refusing to provide exclusive access of the first cache line to the first processor, based on the indication.
Public/Granted literature
- US20230137467A1 HISTORY-BASED SELECTIVE CACHE LINE INVALIDATION REQUESTS Public/Granted day:2023-05-04
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