公开(公告)号：US20230137467A1

公开(公告)日：2023-05-04

申请号：US17514811

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0891

Abstract: Techniques for performing cache operations are provided. The techniques include recording an indication that providing exclusive access of a first cache line to a first processor is deemed problematic; detecting speculative execution of a store instruction by the first processor to the first cache line; and in response to the detecting, refusing to provide exclusive access of the first cache line to the first processor, based on the indication.

公开(公告)号：US20230102891A1

公开(公告)日：2023-03-30

申请号：US17489726

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/123

Abstract: Systems and methods for cache replacement are disclosed. Techniques are described that determine a re-reference interval prediction (RRIP) value of respective data blocks in a cache, where an RRIP value represents a likelihood that a respective data block will be re-used within a time interval. Upon an access, by a processor, to a data segment in a memory, if the data segment is not stored in the cache, a data block in the cache to be replaced by the data segment is selected, utilizing a binary tree that tracks recency of data blocks in the cache.

公开(公告)号：US20150120976A1

公开(公告)日：2015-04-30

申请号：US14522137

申请日：2014-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker ,  Paul J. Moyer ,  Richard M. Born ,  Eric Morton ,  David Christie ,  Marius Evers ,  Scott T. Bingham

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F9/467 ,  G06F9/526 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2209/522 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract translation: 用于执行总线锁定和翻译后备缓冲器无效事务的方法和装置包括由锁定主机接收来自系统中的第一处理器的锁定请求。 锁定主机向系统中的所有处理器发送静默请求，并且在收到来自锁定主机的停顿请求后，所有处理器都停止发出任何新的事务并发出静默授权交易。 在从所有处理器接收到暂停许可的交易之后，锁定主机发出包含第一处理器的标识符的锁授予消息。 第一个处理器执行原子事务序列，并在原子事务序列完成时向锁主机发送第一个锁定释放消息。 当从第一处理器接收到第一锁定释放消息时，锁定主机向所有处理器发送第二锁定释放消息。

公开(公告)号：US11947455B2

公开(公告)日：2024-04-02

申请号：US18135555

申请日：2023-04-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

公开(公告)号：US11836085B2

公开(公告)日：2023-12-05

申请号：US17514792

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0891 ,  G06F9/30 ,  G06F12/0831

CPC classification number: G06F12/0891 ,  G06F9/30043 ,  G06F9/30047 ,  G06F12/0833

Abstract: Techniques for performing cache operations are provided. The techniques include, recording an entry indicating that a cache line is exclusive-upgradeable; removing the cache line from a cache; and converting a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.

公开(公告)号：US11768778B2

公开(公告)日：2023-09-26

申请号：US17490820

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/00 ,  G06F12/123

CPC classification number: G06F12/123 ,  G06F2212/1044

Abstract: Techniques for performing cache operations are provided. The techniques include tracking re-references for cache lines of a cache, detecting that eviction is to occur, and selecting a cache line for eviction from the cache based on a re-reference indication.

公开(公告)号：US20230100230A1

公开(公告)日：2023-03-30

申请号：US17488206

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0897 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/02

Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.

公开(公告)号：US11860787B2

公开(公告)日：2024-01-02

申请号：US17490739

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Ciji Isen ,  Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/02

CPC classification number: G06F12/0811 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0862 ,  G06F2212/1021

Abstract: Methods, devices, and systems for retrieving information based on cache miss prediction. A prediction that a cache lookup for the information will miss a cache is made based on a history table. The cache lookup for the information is performed based on the request. A main memory fetch for the information is begun before the cache lookup completes, based on the prediction that the cache lookup for the information will miss the cache. In some implementations, the prediction includes comparing a first set of bits stored in the history table with a second set of bits stored in the history table. In some implementations, the prediction includes comparing at least a portion of an address of the request for the information with a set of bits in the history table.

公开(公告)号：US20230136114A1

公开(公告)日：2023-05-04

申请号：US17514792

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0891 ,  G06F12/0831 ,  G06F9/30

Abstract: Techniques for performing cache operations are provided. The techniques include, recording an entry indicating that a cache line is exclusive-upgradeable; removing the cache line from a cache; and converting a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.

公开(公告)号：US11630772B1

公开(公告)日：2023-04-18

申请号：US17489702

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0802

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.